1. Field of the Invention
The present invention relates to a display device. More particularly, the present invention relates to a display device and a driving circuit using a control method for eliminating deficient display.
2. Description of Related Art
With the development of the optoelectronic and semiconductor technology, there is a rapid development in the field of panel displays. Among various kinds of panel displays, the thin film transistor liquid crystal displays (TFT-LCDs) having the features of high space utilization efficiency, low power consumption, no radiation and low electromagnetic interference become popular in the market recently. Since the TFT-LCD is widely used in the electronic products such as notebook computers, cell phones and televisions etc., improvement of the image quality is a constant goal in the field.
Generally, a special driving method can be applied for preventing an abnormal image display. For example, to avoid a residual image phenomenon occurred while the LCD panel is turned off, an all high function circuit is allocated in the gate driver for generating a control signal to control the gate driver outputting a high level to all scan lines, while the display panel is detected to be turned off. Therefore, all the thin film transistors corresponding to pixels or sub-pixels on the panel are synchronously turned on, so as to form a discharge path to accelerate the discharge of the capacitors of the pixels or sub-pixels, and eliminate the residual image phenomenon occurred while the display panel is turned off.
FIG. 1 is a block diagram of a gate driver of a conventional LCD. Referring to FIG. 1, the gate driver includes a shift register 101, a level shifter 102 and an output buffer 103. A timing controller (not shown) generates a vertical clock signal VCLK to control the state outputting time of each stages of shift register units in the shift register 101 for sequentially outputting an on/off logic states for each corresponding scan line. The level shifter 102 instantaneously converts the low voltage logic level to a high turn-on voltage and low turn-off voltage required for turning on/off of the film transistors on the panel. However, if the scan lines are driven directly by an output of the level shifter 102, the driving capability may be insufficient, therefore an output buffer 103 is added for increasing the driving capability.
In addition, a control signal OE is used for controlling the turn-on time of the film transistors. The signal XON is a control signal generated while the display panel is detected to be turned off, and the signal XON is used to control all of the output terminals Y1˜Yn of the gate driver outputting a logic high level, in order to turn on all of the film transistors on the panel scan lines. Therefore, the signal XON is generally synchronous to a signal indicating that voltages are dropped, namely, if the system voltage is less than a predefined voltage while the display panel is turned off, the signal XON will be transmitted to the gate driver to accelerate the discharge of the capacitors of the pixels or sub-pixels in the panel.
FIG. 2 is a block diagram of a source driver of a conventional LCD. Referring to FIG. 2, the source driver includes a shift register 201, a line latch 202, a level shifter 203, a digital to analog converter 204, an output buffer 205, a data register 206 and a signal receiver 207, wherein the operation of the shift register 201, level shifter 203 and output buffer 205 has been described in FIG. 1, and the repeated description will be omitted hereby.
The signal receiver 207 receives a digital video data, and stores the digital video data in the data register 206. A timing controller (not shown) generates a horizontal clock signal HCLK to control the state outputting time of each stage of shift register units in the shift register 201 for sequentially storing all of the digital video data to be displayed on the scan line pixels in the line latch 202. The digital to analog converter 204 converts the digital video data into corresponding pixel voltages, in which a polarity signal (POL) inverses each time within each scan line cycle to inverse the output polarity of the adjacent scan lines, and the signal CLK1 is an control signal for controlling the output of the source driver.
In addition, the two ends of each switch in the first switching group 208 are respectively connected to an output terminal X1˜Xn of the source driver and a connecting terminal Z1˜Zn of the panel data line, wherein the signal CON controls the on/off state of the first switching group 208 to output the pixel voltages to the panel data lines, therefore the signal CON can be the signal CLK1 or a signal synchronous with the signal CLK1.
According to the aforementioned description of the gate driver and the source driver, FIG. 3 is a block diagram of a conventional LCD, in which a plurality of source driver is coupled to the data lines of the LCD panel 303, and a plurality of gate driver is coupled to the scan lines of the LCD panel 303. For example, the connecting terminals 302 of the source drivers 301a, 301b, 301c shown in FIG. 3 are coupled to the data lines of the LCD panel 303, the output terminals 305 of the gate drivers 304a and 304b are coupled to the scan lines of the LCD panel 303. The timing controller 306 provides control signals CLK1 and POL to the source drivers 301a, 301b, 301c. A voltage detector 307 is used for detecting the system voltage Vsystem, and if the system voltage Vsystem is less than a predefined voltage, a control signal XON is provided to control the output terminals 305 of the gate drivers 304a and 304b outputting a high level, so as to turn on all the film transistors on the scan lines of the LCD panel 303 to accelerate the discharge of the capacitors of the pixels or sub-pixels in the LCD panel 303.
However, while all the film transistors are turned on, the source drivers maybe still connect to the data lines, and each outputting level of the source drivers maybe has a different state (or level), this may cause a block mura phenomenon on the LCD panel when the LCD panel is turned off. FIG. 4 is a timing diagram of the correlative control signals of a source driver and a gate driver. Referring to FIG. 4, if the system voltage Vsystem is less than a predefined voltage (i.e. the display panel is turned off), the output terminals Y1˜Yn (shown as FIG. 1) of the gate driver synchronously output a high level (shown as block 402). Since the control signals CLK1 and POL for controlling the output of source drivers are respectively in an unknown state 403 and 404, wherein the control signal CLK1 (described as FIG. 2) also controls the switch of the first switching group 208, therefore the connecting terminal Z1˜Zn of the source drivers are also in an unknown state 401. In other words, when all the film transistors on the panel scan lines are turned on, different voltage of each data line will cause a corresponding different discharging speed of the capacitors of the pixels or sub-pixels on the panel, and accordingly, a block mura phenomenon occurs when the display panel is turned off.